In computer architecture, a processor register is a very fast computer memory used to speed the execution of computer programs by providing quick access to commonly used values-typically, the values being in the midst of a calculation at a given point in time.
These registers are the top of the memory hierarchy, and are the fastest way for the system to manipulate data. In a very simple microprocessor, it consists of a single memory location, usually called an accumulator. Registers are built from fast multi-ported memory cell. They must be able to drive its data onto an internal bus in a single clock cycle. The result of ALU operation is stored here and could be re-used in a subsequent operation or saved into memory.
Registers are normally measured by the number of bits they can hold, for example, an “8-bit register” or a “32-bit register”. Registers are now usually implemented as a register file, but they have also been implemented using individual flip-flops, high speed core memory, thin film memory, and other ways in various machines.
The term is often used to refer only to the group of registers that can be directly indexed for input or output of an instruction, as defined by the instruction set. More properly, these are called the “architected registers“. For instance, the x86 instruction set defines a set of eight 32-bit registers, but a CPU that implements the X86 instruction set will contain many more hardware registers than just these eight.
There are several other classes of registers:
(a) Accumulator: It is most frequently used register used to store data taken from memory. Its number varies from microprocessor to microprocessor.
(b) General Purpose registers: General purpose registers are used to store data and intermediate results during program execution. Its contents can be accessed through assembly programming.
(c) Special purpose Registers: Users do not access these registers. These are used by computer system at the time of program execution. Some types of special purpose registers are given below:
- Memory Address Register (MAR): It stores address of data or instructions to be fetched from memory.
- Memory Buffer Register (MBR): It stores instruction and data received from the memory and sent from the memory.
- Instruction Register (IR): Instructions are stored in instruction register. When one instruction is completed, next instruction is fetched in memory for processing.
- Program Counter (PC): It counts instructions.
The instruction cycle is completed into two phases: (a) Fetch Cycle and (b) Execute Cycle. There are two parts in instruction- opcode and operand. In fetch cycle opcode of instruction is fetched into CPU. The opcode, at first, is reached to Data Register (DR), then to Instruction Register (IR). Decoder accesses the opcode and it decodes opcode and type of operation is declared to CPU and execution cycle is started.
RISC and CISC:
The RISC and CISC are technologies on which on which design and architecture of microprocessor is based.
- RISC: It stands for Reduced Instruction Set Computer in which each instruction has dedicated electronic circuitry made from gates, decoders etc to generate control signal. It is a hardwired technique of designing processor unit. Example: DEC’s Alpha, Power PC, ULTRASPARC
- CISC: It stands for Complex Instruction Set Computer based on microprogramming techniques. The hardware is controlled by instructions coded in control memory. Instruction is called microinstruction and coding process is called microprogramming. Each microinstructions produces control signal to control hardware of computer. CISC is more complex but less efficient processor designing technique.
Example: Intel 80486, Pentium I, Pentium II, Celeron, Pentium III
Difference between RISC and CISC:
|Small set of instruction with fixed (32 bits) format and most register based instructions.||Large set of instructions with variable format (16-64 bits per instructions)|
|2.||Addressing modes are limited to 3-5||12-24 addressing modes|
|3.||Large numbers (32-192) of GPRs (General Purpose Registers) with mostly split data cache and instruction cache.||8-24 GPRs with a unified cache for instruction and data, recent designs also use split caches.|
|4.||Most hardwired without control memory.||Most micro-coded using memories (ROM), but modern CISC also use hardwired control.|
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